FIG. 1 shows a portion of a dynamic random access memory (DRAM) device 10. DRAM 10 includes a plurality of dynamic memory cells or units 12, a plurality of row or word lines 14, and a plurality of column or bit lines 16. Only two memory cells 12, two row lines 14, and two column lines 16 are shown in FIG. 1.
The dynamic memory cells of DRAM 10 are arranged in memory array columns which each include numerous memory cell pairs such as the single pair shown. Each column might contain, for example, 1024 or 2048 pairs of memory cells. Each memory cell 12 comprises a storage capacitor or cell 20 and an access switch or device 22 which is preferably an n-channel metal oxide semiconductor field effect transistor (n-MOSFET).
Dynamic memory cell 20 is operated by and with reference to upper and lower supply voltages. The lower supply voltage is typically referred to as ground, while the upper voltage is referred to as V.sub.cc. A first side or cell plate of storage cell 20 is connected to an intermediate reference voltage between V.sub.cc and ground. This reference voltage is typically equal to V.sub.cc /2, or the average of the upper and lower memory cell supply voltages. It is produced by a cell plate generator circuit, and is referred to as DVC2. The first cell plates of all storage cells 20 are typically formed by a single conducting layer within memory device 10, and therefore all are connected to DVC2 at a common electrical potential.
A second side or plate of storage cell 20 is connected to one active terminal of access device 22. One of column lines 16 is connected to the other active terminal of access device 22. The gate or control terminal of access device 22 is connected to one of row lines 14. Each memory unit 12 is therefore connected to both a row line 14 and a column line 16.
The row lines and column lines form a two-dimensional matrix having a plurality of intersections. A single memory cell 12 corresponds to each intersection between a row line and a column line. At a single such intersection, a row line is connected to selectively activate the corresponding memory unit. Activating the memory unit connects the memory units storage capacitor to the corresponding column line to allow conventional memory access operations such as reading, writing, or refreshing.
Memory device 10 utilizes what is commonly referred to as a "folded" column line configuration, wherein each pair of column lines is associated with only a single positive sense amplifier (not shown), a single negative sense amplifier (not shown) and a single column line equilibrate circuit 30. Each equilibrate circuit 30 includes a pair of equilibrate transistors 32. One active terminal of each equilibrate transistor is connected to receive the cell plate reference voltage DVC2. The other active terminal of each equilibrate transistor 32 is connected to one of the adjacent column lines 16. Equilibrate circuits 30 are responsive to an equilibrate signal EQ to simultaneously connect reference voltage DVC2 to the column lines. During normal memory access operations, equilibrate signal EQ is activated to "pre-charge" the column lines to intermediate reference voltage DVC2 prior to activating transfer devices 22 and accessing memory cells.
The memory functions of memory device 10 are performed by storage cells 20. The first cell plate of each storage cell is maintained at a non-varying intermediate voltage-reference voltage DVC2. The second cell plate is charged to either the upper supply voltage (V.sub.cc) or the lower supply voltage (ground), depending on whether a binary 1 or 0 is being written to the cell. Reading a memory cell is performed by detecting whether the memory cell's second plate is above or below the intermediate reference voltage.
FIG. 2 shows a typical cell plate generator circuit 40 for producing reference voltage DVC2. In normal operation, cell plate generator 40 produces reference voltage DVC2 at a nominal intermediate operating value approximately midway between V.sub.cc and ground. Cell plate generator 40 includes a first or upper group 42 of voltage dividing p-MOSFET (p-channel metal oxide semiconductor field effect transistor) transistors 44. Cell plate generator 40 also includes a second or lower group 46 of voltage dividing n-MOSFET (n-channel MOSFET) transistors 48. Transistors 44 and 48 are relatively small so that they have appreciable resistance at relevant operating currents. The transistors of each group are connected in series with each other, and the two transistor groups are connected in series between the upper memory cell supply voltage (V.sub.cc) and the lower memory cell supply voltage (ground). The transistors thus form a voltage divider between V.sub.cc and ground.
A pair of diode-connected n-MOSFET transistors 50 and 52 are connected in series between the two groups of voltage dividing transistors. This forms first and second intermediate voltage divider nodes 54 and 56 in cell plate generator 40. First intermediate node 54 is maintained at a somewhat higher voltage than second intermediate node 56 by the diode-connected transistors. Diodes 50 and 52 ensure that first intermediate voltage divider node 54 is always at a somewhat higher voltage than second intermediate voltage divider node 56.
Cell plate generator 40 includes an output stage comprising a complementary pair of output transistors 58 and 60. n-MOSFET driver transistor 58 has its gate connected to first intermediate node 54, and p-MOSFET driver transistor 60 has its gate connected to second intermediate node 56. The drain of n-MOSFET driver transistor 58 is connected to V.sub.cc. The drain of p-MOSFET driver transistor 60 is connected to ground. The sources of the two transistors are connected together to supply reference voltage DVC2. Thus, the voltage divider formed by the first and second group of voltage dividing transistors determines and establishes the value of DVC2. Transistors 44 and 48 must be carefully designed and manufactured to establish the correct value for DVC2. In some designs, individual voltage dividing transistors can be removed or disabled during product development to "tune in" the cell plate generator so that it produces an optimum value for DVC2.
Cell plate generator 40 includes feedback to regulate DVC2 in response to changing current requirements. This feedback is implemented by connecting the gates of voltage-dividing transistors 44 and 48 to DVC2. With this connection, a decrease in the voltage of DVC2 decreases the effective resistance of first voltage-dividing transistors 44 while increasing the effective resistance of second voltage-dividing transistors 48. This in turn increases the current supplying ability of the generator and raises the value of DVC2. An increase in the voltage of DVC2 increases the effective resistance of first voltage-dividing transistors 44 while decreasing the effective resistance of second voltage-dividing transistors 48. This in turn decreases the current supplying ability of the generator and lowers DVC2. This regulates DVC2 to correct for changing current demands placed on the cell plate generator.
The value and stability of DVC2 is very important to correct DRAM operation, since all memory read/write operations use DVC2 as a reference. Nevertheless, small variations in DVC2 are expected, and memory cells must allow for such variations. In fact, adequate tolerance for DVC2 variations is very important for correct and reliable DRAM operation. Accordingly, DRAM testing procedures frequently and desirably include extensive verification and determination of DVC2 margins allowed by each chip and the various components of each chip without resulting in memory errors.
For this reason, cell plate generator 40 includes provisions for changing reference voltage DVC2 during probe testing. Specifically, cell plate generator 40 is responsive to a test mode signal FLOAT to float or present a high impedance at the output node which is formed between driver transistors 58 and 60. The FLOAT signal is connected to the gate of a first cut-off p-MOSFET transistor 62. Transistor 62 is connected in series between V.sub.cc and the first group 42 of voltage dividing transistors to disconnect the voltage divider circuit from V.sub.cc in response to the FLOAT signal. The FLOAT signal is also connected to the gate of an n-MOSFET grounding transistor 64. Grounding transistor 64 is connected from first intermediate node 54 to ground so that it turns off n-MOSFET driver transistor 58 in response to the FLOAT signal. Similar transistors 66 and 68 are used to turn off p-MOSFET driver transistor 60 and to disconnect the voltage divider circuit from ground in response to the FLOAT signal. An inverter circuit 70 provides an inverted form of the FLOAT signal to the gates of these transistors. The FLOAT signal therefore "turns off" the cell plate generator and allows DVC2 to "float."
Cell plate generator 40 also includes a test pad or probe access point 72 which is accessible during probe testing to directly control the value of reference voltage DVC2 with external testing equipment. DVC2 is varied by such equipment over a specified range of test voltages to test individual dies, before packaging, for acceptable reference voltage margins. An acceptable DRAM chip should operate correctly over a range of reference voltage values.
Testing by manipulating DVC2 has been performed during wafer-level probe testing. It has also been performed after chip packaging. Such margin testing is typically performed for diagnostic purposes on chips which have failed the extensive tests which follow packaging. In order to perform such testing, the package must be destructively removed or etched away from over the internal die to allow access to probe access points such as probe access point 72 of cell plate generator 40.
While post-packaging diagnostic testing has been used at times in the past, newer methods of chip packaging have made the practice much more difficult-if not impossible. Leads over chip (LOC) packaging technology, specifically, has complicated the task of exposing die test pads and probe access points once the die has been packaged.
FIG. 3 shows a packaged integrated circuit (IC) 74 utilizing LOC technology. IC 74 contains a DRAM die 76, encased in a plastic package 78. The top of package 78 is partially broken away in FIG. 3 to show internal components such as die 76. LOC-packaged IC 74 differs from more conventional ICs in that its lead frame is physically laminated to the face of die 76. Specifically, leads 80 are laminated to the face of die 76 with strips of double-sided adhesive film 82. Inner ends of leads 80 extend over the die face, to nearly the center of die 76. A narrow path 84 of die 76, generally along its longitudinal centerline, is left exposed for placement of bonding pads. Conventional wire-bond connections 86 extend between leads 80 and bonding pads within narrow path 84.
While this type of IC packaging provides a number of readily apparent advantages, it practically rules out the possibility of post-packaging diagnostic testing using test probes. The central wire bonds and chip leads overlying the die face leave no room for probe access. Furthermore, the leads and various bonds and bonding materials cannot be conveniently removed to allow probe access. Thus, a valuable diagnostic tool is lost when leads over chip packaging is utilized.
However, the invention described below allows post-packaging DVC2 margin testing even when LOC packaging technology is used. Additionally, it allows DVC2 margin testing to be performed on every packaged DRAM chip, as a routine part of packaged part production testing. Routine margin testing of all packaged chips had previously been impractical, since it required destructively removing portions of chip packaging. The invention, however, allows DVC2 margin testing of packaged parts. It thus allows a much wider range of post-packaging acceptance and diagnostic testing than has previously been possible.